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논문 기본정보
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
논문 개요
| 기관명 | NDSL |
|---|---|
| 저널명 | Journal of semiconductor technology and science |
| ISSN | 1598-1657, |
| ISBN |
논문저자 및 소속기관 정보
| 저자(한글) | Han, Sangwoo,Lim, Jongtae,Kim, Jongsun |
|---|---|
| 저자(영문) | |
| 소속기관 | |
| 소속기관(영문) | |
| 출판인 | |
| 간행물 번호 | |
| 발행연도 | 2016-01-01 |
| 초록 | A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$ . The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz. |
| 원문URL | http://click.ndsl.kr/servlet/OpenAPIDetailView?keyValue=03553784&target=NART&cn=JAKO201608450940823 |
| 첨부파일 |
추가정보
| 과학기술표준분류 | |
|---|---|
| ICT 기술분류 | |
| DDC 분류 | |
| 주제어 (키워드) | DLL,multiplying DLL,MDLL,frequency multiplier,clock multiplier,multi-phase clock |