시설장비 설명 |
An 8x8-Gb/s/channel 4-PAM transceiver was designed for high speed memory applications by using 70nm DRAM process with 1.35V supply. An asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margin of upper and lower eyes in 3-class eye opening. A mathematical basis shows that this scheme statistically reduces 33% of reference noise effect in a receiver. Also an adaptive pre-emphasis scheme which utilizes a lone-bit pulse with integrator at the receiver is introduced to reduce ISI for a simple DRAM channel. In this scheme an integrating clock timing calibration by using a pre-determined pattern is proposed for the optimum ISI measurement. |