| 시설장비 설명 |
Microarchitecture based on 14 nanometer manufacturing process • Based on Intel® Silvermont with HPC enhancements • 4 Threads / Core • Deep out-of-order buffers • Gather/scatter in hardware • Advanced branch prediction • 2D Core mesh architecture • Binary compatible with Intel® Xeon® Processors • Standalone bootable processor (running the host OS) and a PCIe coprocessor • Integrated high performance on-package memory (MCDRAM library) • Flexible memory modes for the on package memory including cache and at • Support for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) • 70+ cores, 3+ TeraFLOPS of double-precision peak theoretical performance per single socket node • No MPSS on KNL bootable processor - everything running natively • Binary compatibility with Xeon (except TSX) •AKA ‘on-package memory’, ‘high-bandwidth memory’, MCDRAM • > 400 GB/s • Up 16GB (at launch) • NUMA support • Over 5x energy efciency, 3x density vs. GDDR5 • Multiple usage models, including ‘L3 cache’ and ‘at’ • Direct memory allocation can be coordinated with use of memkind library |
